A Design of Input-Decimation Technique for Recursive DFT/IDFT Algorithm

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 66; no. 12; pp. 4713 - 4726
• Main Authors: Wu, Chih-Feng, Chen, Chun-Hung, Shiue, Muh-Tian
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Array signal processing; Broadband; CMOS; Communications systems; Computational efficiency; Computer architecture; Computing time; constant multiplier; Discrete Fourier transform (DFT); Discrete Fourier transforms; Fourier transforms; High speed; IIR filters; input-decimation; Multiplication; OFDM; Power consumption; Receivers; recursive DFT (RDFT); recursive inverse DFT (RIDFT); Sequences; Signal processing algorithms
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2019.2931794

In this paper, an input-decimation technique for the recursive discrete Fourier transform (RDFT)/inverse DFT (RIDFT) algorithm is proposed for the high-speed broadband communication systems. It is worth noting that the input-decimation approach is presented to decrease the number of input sequences for the recursive filter so that the computation cycle of RDFT/RIDFT can be shortened to meet the computing time requirement (3.6 μs) for the high-speed broadband communication systems. Therefore, the input-decimation RDFT/RIDFT algorithm is able to carry out at least 55.5% reduction of the total computation cycles compared with the considered algorithms. Furthermore, holding the advantages of input-decimation technique, the computational complexities of the real-multiplication and -addition are reduced to 41.3% and 22.2%, respectively. The area and the power consumption can be minimized by employing the cost-efficient constant multiplier with the refined signed-digit expression of twiddle factors. Finally, the physical implementation results show that the core area is 0.37×0.37 mm2 with 0.18 μm CMOS process. The power consumption is 5.16 mW with the supply voltage of 1.8 V and the operating clock of 40 MHz. The proposed design can achieve 258 million of computational efficiency per unit area (CEUA) and really outperform the previous works.