A Scalable Compact Model for the Static Drain Current of Graphene FETs

• Published in: IEEE transactions on electron devices Vol. 71; no. 1; pp. 1 - 7
• Main Authors: Mavredakis, Nikolaos, Pacheco-Sanchez, Anibal, Txoperena, Oihana, Torres, Elias, Jimenez, David
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit design; Circuits; compact model; contact resistance; Field effect transistors; flat-band voltage; geometrical scaling; Graphene; graphene field-effect transistor (GFET); mobility; residual charge; Semiconductor devices
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2023.3330713

The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures I-V experimental dependencies induced by geometrical scaling effects for graphene field-effect transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions are thoroughly investigated, and semi-empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in research laboratory. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and, hence, can contribute to the update of GFET technology from the research level to massive industry production.