High Speed Digital Distance Relaying Scheme Using FPGA and IEC 61850

• Published in: IEEE transactions on smart grid Vol. 9; no. 5; pp. 4383 - 4393
• Main Authors: Jin, Xingxing, Gokaraju, Ramakrishna, Wierckx, Rudi, Nayak, Om
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.09.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: adaptive protection; Computer simulation; Decision analysis; Estimation; Ethernet; Field programmable gate arrays; Filtration; FPGAs; Gate arrays; Hardware-in-the-loop simulation; hardware-in-the-loop simulations; Harmonic analysis; High voltages; IEC 61850; Indexes; Numerical methods; Parallel processing; Power harmonic filters; Probability density function; Relaying; Response time; Sub-cycle algorithms; Time domain analysis; Transient analysis; Traveling waves; Trip estimation; Wavelet analysis
• ISSN: 1949-3053; 1949-3061
• DOI: 10.1109/TSG.2017.2655499

Full-cycle Fourier and cosine phasor filtering systems are typical implementations of numerical distance relays with a response time of close to one cycle. Fast subcycle numerical distance elements are useful, especially for extra high voltage/UHV transmission systems (400 kV and above). Fast subcycle numerical relaying methods such as half-cycle Fourier method, phaselets, least error squares, traveling wave, and wavelet based methods have been proposed in the literature. In this paper, first improvements to the phaselet-based distance relaying method are proposed by taking the magnitude errors and the phase angle errors into account. An adaptive Mho characteristic based on the phasor estimation errors is used to achieve a fast and secure trip decision. The quality of the estimated values in time domain is analyzed mathematically using a transient monitoring index. Second, the scheme is implemented on a field programmable gate arrays (FPGAs) board, which provides fast computation speeds due to its powerful parallel processing units. The proposed relay is tested using hardware-in-the-loop simulations and a real time digital simulator. Third, the Ethernet-based protocols (IEC 61850 sampled value and generic object oriented substation events protocols) are implemented on the FPGA and used to verify the performance of the proposed relay in digital substation environments.