Review on SiC MOSFETs High-Voltage Device Reliability Focusing on Threshold Voltage Instability

• Published in: IEEE transactions on electron devices Vol. 66; no. 11; pp. 4604 - 4616
• Main Authors: Puschkarsky, K., Grasser, T., Aichinger, T., Gustin, W., Reisinger, H.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bias temperature instability (BTI); capture–emission-time (CET); Circuits; high temperature gate stress (HTGS); hysteresis; Logic gates; Measurement techniques; Modelling; MOSFET; MOSFETs; Reliability; SiC; Silicon; Silicon carbide; Stress; Stress measurement; Threshold voltage; Voltage measurement
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2019.2938262

An overview over issues and findings in SiC power MOSFET reliability is given. The focus of this article is on threshold instabilities and the differences to Si power MOSFETs. Measurement techniques for the characterization of the threshold voltage instabilities are compared and discussed. Modeling of the threshold voltage instabilities based on capture-emission-time (CET) maps is a central topic. This modeling approach takes the complete gate bias/temperature history into account. It includes both gate stress polarities and is able to reproduce the short-term threshold variations during application-relevant 50-kHz bipolar ac-stress. In addition, the impact on circuit operation is discussed.