Circulating Current Reduction for Paralleled Inverters With Modified Zero-CM PWM Algorithm

• Published in: IEEE transactions on industry applications Vol. 54; no. 4; pp. 3518 - 3528
• Main Authors: Shen, Zewei, Jiang, Dong, Chen, Jianan, Qu, Ronghai
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.07.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Common mode voltage (CMV); Computer simulation; Coupled modes; Design modifications; differential-mode circulating current (DMCC); Frequency modulation; Inductors; Inverters; Modulation; paralleled inverters; Pulse width modulation; pulsewidth modulation; Reduction; Switches; Switching frequency; zero-sequence circulating current (ZSCC)
• ISSN: 0093-9994; 1939-9367
• DOI: 10.1109/TIA.2018.2821653

Paralleled inverters are not only a suitable approach to increase the power capacity, but also have the capability of common mode voltage (CMV) reduction, or even elimination. The original zero CMV modulation scheme for paralleled inverters suffers from the current jump problem in phase-leg currents. This current jump phenomenon amplifies the peak values of differential-mode circulating current (DMCC) and zero-sequence circulating current (ZSCC), which is adverse for the design of coupled inductor and common-mode inductor. This paper introduces the modified modulation scheme, which can keep volt-seconds balance in whole fundamental period and mitigate the current jump in phase-leg currents. In addition, the reduction effect of the DMCC and ZSCC can be achieved. To verify the analysis, both the simulation and experimental results are presented, which validates the proposed methods and show that they are beneficial for DMCC and ZSCC reduction.