Finite-word-length FPGA implementation of model predictive control for ITER resistive wall mode control

• Published in: Fusion engineering and design Vol. 169; p. 112480
• Main Authors: Gerkšič, Samo, Pregelj, Boštjan
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.08.2021; Elsevier Science Ltd
• Subjects: Active control; Algorithms; Control algorithms; Fast gradient method; Feedback control; Field programmable gate arrays; FPGA; Optimization; Personal computers; Plasma magnetic control; Plasma pressure; Predictive control; Quadratic programming; Tokamak devices; Fast gradient method; Plasma magnetic control; Quadratic programming; FPGA; Predictive control
• ISSN: 0920-3796; 1873-7196
• DOI: 10.1016/j.fusengdes.2021.112480

•A fast implementation of model predictive control is presented.•The primal fast gradient method is used for online optimization.•Finite-word-length arithmetic is efficient for FPGA implementation.•A high-level synthesis approach for FPGA programming is used.•The approach is tested using a Xilinx Alveo U250 accelerator card. In advanced tokamak scenarios, active feedback control of unstable resistive wall modes (RWM) may be required. A RWM is an instability due to plasma kink at higher plasma pressure, moderated by the presence of a resistive wall surrounding the plasma. We address the dominant kink instability associated with the main non-axisymmetric (n = 1) RWM, described by the CarMa model. Model predictive control (MPC) is used, with the aim of enlarging the domain of attraction of the unstable RWM modes subject to power-supply voltage constraints. The implementation of MPC is challenging, because the related quadratic programming (QP) on-line optimization problems must be solved at a sub-ms sampling rate. Using complexity-reduction pre-processing techniques and a primal fast gradient method (FGM) QP solver, sufficiently short computation times for ITER are reachable using a standard personal computer (PC). In this work we explore even faster finite-word-length (FWL) implementation using field-programmable gate arrays (FPGA), which would facilitate experimental testing of such control algorithms on dynamically faster medium-sized tokamaks, and compare the computational accuracy and time with the PC implementation.