Low-Complexity Architecture for High-Speed 50G-PON LDPC Decoder

• Published in: IEEE access Vol. 13; pp. 28751 - 28765
• Main Authors: Kwon, Kon-Woo, Kim, Kwangok, Doo, Kyeonghwan, Chung, Hwanseok, Lee, Jeong Woo
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 50G-PON; Algorithms; architecture; Columnar structure; Complexity; Computer architecture; Decoding; Error correcting codes; Error correction; FPGA; Hardware; High speed; high throughput; Iterative decoding; LDPC decoder; low complexity; Modems; Nodes; Parity; Passive optical networks; Resource management; Resource utilization; Throughput; Wiring
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2025.3540450

We propose a hardware architecture for 50G-PON LDPC decoder achieving high throughput and high error correcting capability while maintaining low level of resource utilization and implementation complexity. Our approach employs phased decoding as a key algorithm which effectively balances the competing goals of high throughput and low amount of resource utilization. We also propose a fixed-structured wiring network between variable nodes and check nodes, leveraging the quasi-cyclic property of parity-check matrix to significantly reduce implementation complexity. To further simplify the decoder structure and enhance the throughput, we propose a blockwise column cyclic shift in the parity-check matrix, along with rules for normalizing and quantizing messages generated in decoder. Our design also incorporates a pipelined structure of computation units. By integrating the proposed design schemes, we draw a sophisticated architecture for high-speed and low-complexity LDPC decoder that achieves the seamless decoding throughput of 49.7664 Gbps, even on a single FPGA board.