A novel flash fast-locking digital phase-locked loop: design and simulations

• Published in: IET circuits, devices & systems Vol. 3; no. 5; pp. 280 - 290
• Main Authors: Wagdy, M.F., Cabrales, B.C.
• Format: Journal Article
• Language: English
• Published: Stevenage Institution of Engineering and Technology 01.10.2009; John Wiley & Sons, Inc
• Subjects: Algorithms; Applied sciences; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Comparators; Computer simulation; Design engineering; Design. Technologies. Operation analysis. Testing; Digital; Electric, optical and optoelectronic circuits; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Frequency ranges; Integrated circuits; Phase locked loops; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Frequency locking; Circuit design; Power supply; Power electronics; Algorithm; Implementation; Flash converter; Codec; AD converter; Complementary MOS technology; Digital phase locked loops; Low pass filter; Comparator circuit; Charge pumping; Multistage circuit; Computer aided design
• ISSN: 1751-858X; 1751-8598
• DOI: 10.1049/iet-cds.2008.0342

A flash digital phase-locked loop (DPLL) is designed using 0.18 μm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-2 GHz. The DPLL operation includes two stages: a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump/lowpass filter combination. Design considerations of the flash DPLL circuit components as well as implementation using Cadence design tools are presented. Spectre simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL. By increasing the number of frequency comparators, the lock time is expected to be always less than 100 ns in the above-mentioned frequency range.