50 MHz dual-mode buck DC-DC converter

• Published in: Journal of semiconductors Vol. 37; no. 8; pp. 85 - 89
• Main Author: 张章 王星 余文成 谭烨 杨依忠 解光军
• Format: Journal Article
• Language: English
• Published: 01.08.2016
• Subjects: 反向电流; 电流调节; 转换器; 转换效率
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/37/8/085002

A 50 MHz 1.8/0.9 V dual-mode buck DC-DC converter is proposed in this paper. A dual-mode control for high-frequency DC-DC converter is presented to enhance the conversion efficiency of light-load in this paper. A novel zero-crossing detector is proposed to shut down synchronous rectification transistor NMOS when the inductor crosses zero, which can decrease the power loss caused by reverse current and the trip point is adjusted by regulating IBIAS （BIAS current）. A new logic control for pulse-skipping modulation loop is also presented in this paper, which has advantages of simple structure and low power loss. The proposed converter is realized in SMIC 0.18μm 1-poly 6-metal mixed signal CMOS process. With switching loss, conduction loss and reverse current related loss optimized, an efficiency of 57% is maintained at 10 mA, and a peak efficiency of 71% is measured at nominal operating conditions with a voltage conversion of 1.8 to 0.9 V.