Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits

• Published in: Integration (Amsterdam) Vol. 62; pp. 159 - 169
• Main Authors: Berrima, Safa, Blaquière, Yves, Savaria, Yvon
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01.06.2018; Elsevier BV
• Subjects: Algorithms; Chains; Defect tolerance; Defect tolerant scan chain; Defects; Diagnosis; Integrated circuits; Large area integrated circuit (LAIC); Reconfiguration; Search algorithms; Defect tolerance; Diagnosis; Large area integrated circuit (LAIC); Defect tolerant scan chain
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2018.02.010

A set of routing algorithms is proposed to diagnose multiple defects in a class of reconfigurable and defect tolerant JTAG scan chains. These algorithms find a maximum number of functional elements with a minimum set of paths with an affordable reconfiguration time. A heuristic dichotomic search algorithm is applied on the nonfunctional paths to accurately locate defective elements. Experiments demonstrate that our algorithms accurately pinpoint 99.1% of single defects and 71% of multiple defects when eight defects were randomly injected. They were also successfully applied on a large area integrated circuit where multiple clusters of defects were located. •A large area integrated circuit (LAIC) as a mesh-like network of cells and links.•The LAIC is configured using reconfigurable and defect tolerant JTAG scan chains.•Diagnosis algorithm of stuck-at faults in the scan chains are proposed.