An efficient prime-factor algorithm for the discrete cosine transform and its hardware implementations

• Published in: IEEE transactions on signal processing Vol. 42; no. 8; pp. 1996 - 2005
• Main Authors: Lee, Pei-Zong, Huang, Fang-Yu
• Format: Journal Article
• Language: English
• Published: IEEE 01.08.1994
• Subjects: Algorithm design and analysis; Convolution; Digital signal processing; Discrete cosine transforms; Discrete Fourier transforms; Fast Fourier transforms; Hardware; Signal processing algorithms; Systolic arrays; Very large scale integration
• ISSN: 1053-587X
• DOI: 10.1109/78.301838

The prime-factor decomposition is a fast computational technique for many important digital signal processing operations, such as the convolution, the discrete Fourier transform, the discrete Hartley transform, and the discrete cosine transform (DCT). The authors present a new prime-factor algorithm for the DCT. They also design a prime-factor algorithm for the discrete sine transform based on the prime-factor DCT algorithm. Hardware implementations for the prime-factor DCT are also studied. They are especially interested in the hardware designs which are suitable for the VLSI implementations. They show three hardware designs for the prime-factor DCT, including a VLSI circuit fabricated directly according to the signal-flow graph, a linear systolic array, and a mesh-connected systolic array. These three designs show the trade-off between cost and performance. The methodology, which deals with general (N/sub 1//spl times/ N/sub 2/)-point DCTs, where N/sub 1/ and N/sub 2/ are mutually prime, is illustrated by converting a 15-point DCT problem into a (3/spl times/5)-point 2D DCT problem.< >