Parallel Reconfigurable Computing-Based Mapping Algorithm for Motion Estimation in Advanced Video Coding

• Published in: ACM transactions on embedded computing systems Vol. 11; no. S2; pp. 1 - 18
• Main Authors: Paul, Anand, Jiang, Yung-Chuan, Wang, Jhing-Fa, Yang, Jar-Ferr
• Format: Journal Article
• Language: English
• Published: 01.08.2012
• Subjects: Algorithms
• ISSN: 1539-9087; 1558-3465
• DOI: 10.1145/2331147.2331149

Computational load of motion estimation in advanced video coding (AVC) standard is significantly high and even worse for HDTV and super-resolution sequences. In this article, a video processing algorithm is dynamically mapped onto a new parallel reconfigurable computing (PRC) architecture which consists of multiple dynamic reconfigurable computing (DRC) units. First, we construct a directed acyclic graph (DAG) to represent video coding algorithms in which motion estimation is the focus. A novel parallel partition approach is then proposed to map motion estimation DAG onto the multiple DRC units in a PRC system. This partitioning algorithm is capable of design optimization of parallel processing reconfigurable systems for a given number of processing elements in different search ranges. This speeds up the video processing with minimum sacrifice.