LMS-Based Background Calibration of Bit Weights in SAR ADC Using Reinforcement Learning Optimization
This paper presents a least-mean-square-based (LMS-based) background calibration algorithm with reinforcement learning optimization to calibrate the capacitor mismatch in successive approximation-register (SAR) analog-to-digital converters (ADCs). When calibrating capacitor mismatch, the convergence...
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| Published in | Circuits, systems, and signal processing Vol. 43; no. 3; pp. 1741 - 1754 |
|---|---|
| Main Authors | , , , , |
| Format | Journal Article |
| Language | English |
| Published |
New York
Springer US
01.03.2024
Springer Nature B.V |
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| Online Access | Get full text |
| ISSN | 0278-081X 1531-5878 |
| DOI | 10.1007/s00034-023-02536-7 |
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| Abstract | This paper presents a least-mean-square-based (LMS-based) background calibration algorithm with reinforcement learning optimization to calibrate the capacitor mismatch in successive approximation-register (SAR) analog-to-digital converters (ADCs). When calibrating capacitor mismatch, the convergence speed and stability of the conventional LMS-based algorithm cannot be balanced due to the fixed iteration step size. To improve the calibration effect, nine different iteration step sizes are proposed for calibration. An iteration step size selection strategy is obtained by training the Q-learning algorithm with the conventional LMS-based calibration iteration process. Leading by this strategy, the proposed calibration algorithm performs better convergence speed and stability than the conventional LMS-based calibration algorithm. A 12-bit sub-radix-2 redundant SAR ADC is used to test our proposed calibration algorithm for better evaluation. Behavioral simulations show that the proposed calibration algorithm converges at 0.065 M sampling points, and the standard deviation of the effective number of bits (ENOB) in the convergence state is only 0.034-bit. |
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| AbstractList | This paper presents a least-mean-square-based (LMS-based) background calibration algorithm with reinforcement learning optimization to calibrate the capacitor mismatch in successive approximation-register (SAR) analog-to-digital converters (ADCs). When calibrating capacitor mismatch, the convergence speed and stability of the conventional LMS-based algorithm cannot be balanced due to the fixed iteration step size. To improve the calibration effect, nine different iteration step sizes are proposed for calibration. An iteration step size selection strategy is obtained by training the Q-learning algorithm with the conventional LMS-based calibration iteration process. Leading by this strategy, the proposed calibration algorithm performs better convergence speed and stability than the conventional LMS-based calibration algorithm. A 12-bit sub-radix-2 redundant SAR ADC is used to test our proposed calibration algorithm for better evaluation. Behavioral simulations show that the proposed calibration algorithm converges at 0.065 M sampling points, and the standard deviation of the effective number of bits (ENOB) in the convergence state is only 0.034-bit. This paper presents a least-mean-square-based (LMS-based) background calibration algorithm with reinforcement learning optimization to calibrate the capacitor mismatch in successive approximation-register (SAR) analog-to-digital converters (ADCs). When calibrating capacitor mismatch, the convergence speed and stability of the conventional LMS-based algorithm cannot be balanced due to the fixed iteration step size. To improve the calibration effect, nine different iteration step sizes are proposed for calibration. An iteration step size selection strategy is obtained by training the Q-learning algorithm with the conventional LMS-based calibration iteration process. Leading by this strategy, the proposed calibration algorithm performs better convergence speed and stability than the conventional LMS-based calibration algorithm. A 12-bit sub-radix-2 redundant SAR ADC is used to test our proposed calibration algorithm for better evaluation. Behavioral simulations show that the proposed calibration algorithm converges at 0.065 M sampling points, and the standard deviation of the effective number of bits (ENOB) in the convergence state is only 0.034-bit. |
| Author | Song, Xinyan Meng, Qiao Meng, Yishuo Zong, Chenchen Huang, Yujia |
| Author_xml | – sequence: 1 givenname: Xinyan surname: Song fullname: Song, Xinyan organization: Institute of Radio Frequency and Optoelectronic Integrated Circuits, Southeast University – sequence: 2 givenname: Qiao orcidid: 0000-0002-8075-7171 surname: Meng fullname: Meng, Qiao email: mengqiao@seu.edu.cn organization: Institute of Radio Frequency and Optoelectronic Integrated Circuits, Southeast University – sequence: 3 givenname: Yujia surname: Huang fullname: Huang, Yujia organization: Institute of Radio Frequency and Optoelectronic Integrated Circuits, Southeast University – sequence: 4 givenname: Chenchen surname: Zong fullname: Zong, Chenchen organization: MIIT Key Laboratory of Pattern Analysis and Machine Intelligence, Nanjing University of Aeronautics and Astronautics – sequence: 5 givenname: Yishuo surname: Meng fullname: Meng, Yishuo organization: School of Microelectronics, Xi’an Jiaotong University |
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| Cites_doi | 10.1109/VLSIC.2014.6858371 10.1049/ell2.12659 10.1109/ICMLA.2019.00160 10.1109/JSSC.2014.2364833 10.1109/ICSICT.2018.8564891 10.1109/TCSI.2022.3166792 10.1109/ISCAS51556.2021.9401172 10.1109/JSSC.2017.2656138 10.1109/AIAM54119.2021.00063 10.1109/CICC.2019.8780222 10.1109/TCSI.2011.2123590 10.1109/A-SSCC47793.2019.9056925 10.1007/s00034-022-02266-2 10.1109/CICC.2012.6330694 10.1109/ASSCC.2018.8579318 10.1109/JSSC.2011.2163556 10.1109/ISCAS51556.2021.9401732 |
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| Keywords | LMS-based background calibration Q-learning Capacitor mismatch Iteration step size selection strategy Reinforcement learning SAR ADC |
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| References | W. Liu, P. Huang, Y. Chiu, A 12-bit 50-MS/s 3.3-mW SAR ADC with Background Digital Calibration, in Process of the IEEE 2012 Custom Integrated Circuits Conference (IEEE, 2012), pp. 1–4 H. Fan, Y. Wang, Q. Wei et al., Capacitor recombination algorithm combined with LMS algorithm in 16-bit SAR ADC with redundancy. Circuits Syst Signal Process (2023) TangXLiuJLiSLow-power SAR ADC design: overview and survey of state-of-the-art techniquesIEEE Trans. Circuits Syst. I Regul. Pap.20226962249226210.1109/TCSI.2022.3166792 WangXLiFWangZA simple histogram-based capacitor mismatch calibration in SAR ADCsIEEE Trans. Circuits Syst. II Express Briefs2020671228382842 L. Zhang, J. Wu, Background Calibration in Pipelined SAR ADCs Exploiting PVT-Tracking Metastability Detector, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE, 2021), pp. 1–5 McNeillJAChanKYColnMCWAll-digital background calibration of a successive approximation ADC using the “Split ADC” architectureIEEE Trans. Circuits Syst. I Regul. Pap.2011581023552365288501710.1109/TCSI.2011.2123590 YangYYinTLiuJA low-cost digital calibration scheme for high-resolution SAR ADC using adaptive-LMSElectron. Lett.202258259499512022ElL....58..949Y10.1049/ell2.12659 H. Garvik, C. Wulff, T. Ytterdal, A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip CDAC Calibration, in 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC) (IEEE, 2019), pp. 193–194 Y.-S. Hu, J.-H. Lin, D.-G. Lin et al., An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-assisted SAR ADC with Weight-Split Compensation Calibration, in 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) (IEEE, 2018), pp. 253–256 Z. Lan, L. Dong, X. Jing et al., A 12-Bit 100MS/s SAR ADC with Digital Error Correction and High-Speed LMS-Based Background Calibration, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE, 2021), pp. 1–5 Y.-H. Chung, C.-Y. Hu, C.-W. Chang, A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration, in 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) (IEEE, 2018), pp. 243–246 HongH-KKimWKangH-WA decision-error-tolerant 45 nm CMOS 7b 1 GS/s nonbinary 2b/Cycle SAR ADCIEEE J. Solid-State Circuits20155025435552015IJSSC..50..543H10.1109/JSSC.2014.2364833 ChenLTangXSanyalAA 0.7-V 0.6-μ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\mu $$\end{document}W 100-kS/s low-power SAR ADC with statistical estimation-based noise reductionIEEE J. Solid State Circuits2017525138813982017IJSSC..52.1388C10.1109/JSSC.2017.2656138 A. Bannon, C.P. Hurrell, D. Hummerston et al., An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range, in 2014 Symposium on VLSI Circuits Digest of Technical Papers (IEEE, 2014), pp. 1–2 LiuWHuangPChiuYA 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibrationIEEE J. Solid State Circuits20114611266126722011IJSSC..46.2661L10.1109/JSSC.2011.2163556 DingXZhangLLiuWA pattern extraction based background calibration technique for SAR ADCsIEEE Trans. Circuits Syst. II Express Briefs20226911014 X. Peng, T. Fu, Q. Bao et al., A New Capacitor Mismatch Calibration Technique for SAR ADCs, in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (IEEE, 2018), pp. 1–4 M. Guo, J. Mao, S. -W. Sin et al., A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration, in 2019 IEEE Custom Integrated Circuits Conference (CICC) (IEEE, 2019), pp. 1–4 ZhangLWangPSunJCorrelation-based background calibration of bit weight in SAR ADCs using DAS algorithmIEEE Trans. Circuits Syst. II Express Briefs202168410631067 Y. Sun, Performance of Reinforcement Learning on Traditional Video Games, in 2021 3rd International Conference on Artificial Intelligence and Advanced Manufacture (AIAM) (IEEE, 2021), pp. 276–279 N.L. Kuang, C.H.C. Leung, Performance Effectiveness of Multimedia Information Search Using the Epsilon-Greedy Algorithm, in 2019 18th IEEE International Conference On Machine Learning and Applications (ICMLA) (IEEE, 2019), pp. 929–936 2536_CR9 W Liu (2536_CR12) 2011; 46 X Ding (2536_CR4) 2022; 69 Y Yang (2536_CR19) 2022; 58 L Chen (2536_CR2) 2017; 52 H-K Hong (2536_CR8) 2015; 50 L Zhang (2536_CR21) 2021; 68 JA McNeill (2536_CR14) 2011; 58 2536_CR11 X Wang (2536_CR18) 2020; 67 2536_CR13 2536_CR16 2536_CR15 2536_CR1 2536_CR3 X Tang (2536_CR17) 2022; 69 2536_CR5 2536_CR7 2536_CR10 2536_CR6 2536_CR20 |
| References_xml | – reference: ZhangLWangPSunJCorrelation-based background calibration of bit weight in SAR ADCs using DAS algorithmIEEE Trans. Circuits Syst. II Express Briefs202168410631067 – reference: W. Liu, P. Huang, Y. Chiu, A 12-bit 50-MS/s 3.3-mW SAR ADC with Background Digital Calibration, in Process of the IEEE 2012 Custom Integrated Circuits Conference (IEEE, 2012), pp. 1–4 – reference: N.L. Kuang, C.H.C. Leung, Performance Effectiveness of Multimedia Information Search Using the Epsilon-Greedy Algorithm, in 2019 18th IEEE International Conference On Machine Learning and Applications (ICMLA) (IEEE, 2019), pp. 929–936 – reference: X. Peng, T. Fu, Q. Bao et al., A New Capacitor Mismatch Calibration Technique for SAR ADCs, in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) (IEEE, 2018), pp. 1–4 – reference: HongH-KKimWKangH-WA decision-error-tolerant 45 nm CMOS 7b 1 GS/s nonbinary 2b/Cycle SAR ADCIEEE J. Solid-State Circuits20155025435552015IJSSC..50..543H10.1109/JSSC.2014.2364833 – reference: A. Bannon, C.P. Hurrell, D. Hummerston et al., An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range, in 2014 Symposium on VLSI Circuits Digest of Technical Papers (IEEE, 2014), pp. 1–2 – reference: ChenLTangXSanyalAA 0.7-V 0.6-μ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\mu $$\end{document}W 100-kS/s low-power SAR ADC with statistical estimation-based noise reductionIEEE J. Solid State Circuits2017525138813982017IJSSC..52.1388C10.1109/JSSC.2017.2656138 – reference: WangXLiFWangZA simple histogram-based capacitor mismatch calibration in SAR ADCsIEEE Trans. Circuits Syst. II Express Briefs2020671228382842 – reference: Y.-S. Hu, J.-H. Lin, D.-G. Lin et al., An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-assisted SAR ADC with Weight-Split Compensation Calibration, in 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) (IEEE, 2018), pp. 253–256 – reference: YangYYinTLiuJA low-cost digital calibration scheme for high-resolution SAR ADC using adaptive-LMSElectron. Lett.202258259499512022ElL....58..949Y10.1049/ell2.12659 – reference: Z. Lan, L. Dong, X. Jing et al., A 12-Bit 100MS/s SAR ADC with Digital Error Correction and High-Speed LMS-Based Background Calibration, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE, 2021), pp. 1–5 – reference: M. Guo, J. Mao, S. -W. Sin et al., A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration, in 2019 IEEE Custom Integrated Circuits Conference (CICC) (IEEE, 2019), pp. 1–4 – reference: H. Garvik, C. Wulff, T. Ytterdal, A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip CDAC Calibration, in 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC) (IEEE, 2019), pp. 193–194 – reference: DingXZhangLLiuWA pattern extraction based background calibration technique for SAR ADCsIEEE Trans. Circuits Syst. II Express Briefs20226911014 – reference: Y.-H. Chung, C.-Y. Hu, C.-W. Chang, A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration, in 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) (IEEE, 2018), pp. 243–246 – reference: L. Zhang, J. Wu, Background Calibration in Pipelined SAR ADCs Exploiting PVT-Tracking Metastability Detector, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE, 2021), pp. 1–5 – reference: LiuWHuangPChiuYA 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibrationIEEE J. Solid State Circuits20114611266126722011IJSSC..46.2661L10.1109/JSSC.2011.2163556 – reference: TangXLiuJLiSLow-power SAR ADC design: overview and survey of state-of-the-art techniquesIEEE Trans. Circuits Syst. I Regul. Pap.20226962249226210.1109/TCSI.2022.3166792 – reference: H. Fan, Y. Wang, Q. Wei et al., Capacitor recombination algorithm combined with LMS algorithm in 16-bit SAR ADC with redundancy. Circuits Syst Signal Process (2023) – reference: McNeillJAChanKYColnMCWAll-digital background calibration of a successive approximation ADC using the “Split ADC” architectureIEEE Trans. Circuits Syst. I Regul. Pap.2011581023552365288501710.1109/TCSI.2011.2123590 – reference: Y. Sun, Performance of Reinforcement Learning on Traditional Video Games, in 2021 3rd International Conference on Artificial Intelligence and Advanced Manufacture (AIAM) (IEEE, 2021), pp. 276–279 – ident: 2536_CR1 doi: 10.1109/VLSIC.2014.6858371 – volume: 68 start-page: 1063 issue: 4 year: 2021 ident: 2536_CR21 publication-title: IEEE Trans. Circuits Syst. II Express Briefs – volume: 69 start-page: 10 issue: 1 year: 2022 ident: 2536_CR4 publication-title: IEEE Trans. Circuits Syst. II Express Briefs – volume: 58 start-page: 949 issue: 25 year: 2022 ident: 2536_CR19 publication-title: Electron. Lett. doi: 10.1049/ell2.12659 – ident: 2536_CR10 doi: 10.1109/ICMLA.2019.00160 – volume: 50 start-page: 543 issue: 2 year: 2015 ident: 2536_CR8 publication-title: IEEE J. Solid-State Circuits doi: 10.1109/JSSC.2014.2364833 – ident: 2536_CR15 doi: 10.1109/ICSICT.2018.8564891 – volume: 69 start-page: 2249 issue: 6 year: 2022 ident: 2536_CR17 publication-title: IEEE Trans. Circuits Syst. I Regul. Pap. doi: 10.1109/TCSI.2022.3166792 – ident: 2536_CR11 doi: 10.1109/ISCAS51556.2021.9401172 – volume: 52 start-page: 1388 issue: 5 year: 2017 ident: 2536_CR2 publication-title: IEEE J. Solid State Circuits doi: 10.1109/JSSC.2017.2656138 – ident: 2536_CR9 – ident: 2536_CR16 doi: 10.1109/AIAM54119.2021.00063 – ident: 2536_CR7 doi: 10.1109/CICC.2019.8780222 – volume: 58 start-page: 2355 issue: 10 year: 2011 ident: 2536_CR14 publication-title: IEEE Trans. Circuits Syst. I Regul. Pap. doi: 10.1109/TCSI.2011.2123590 – ident: 2536_CR6 doi: 10.1109/A-SSCC47793.2019.9056925 – volume: 67 start-page: 2838 issue: 12 year: 2020 ident: 2536_CR18 publication-title: IEEE Trans. Circuits Syst. II Express Briefs – ident: 2536_CR5 doi: 10.1007/s00034-022-02266-2 – ident: 2536_CR13 doi: 10.1109/CICC.2012.6330694 – ident: 2536_CR3 doi: 10.1109/ASSCC.2018.8579318 – volume: 46 start-page: 2661 issue: 11 year: 2011 ident: 2536_CR12 publication-title: IEEE J. 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| SubjectTerms | Algorithms Analog to digital converters Calibration Capacitors Circuits and Systems Convergence Electrical Engineering Electronics and Microelectronics Engineering Instrumentation Machine learning Optimization Signal,Image and Speech Processing Stability |
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| Title | LMS-Based Background Calibration of Bit Weights in SAR ADC Using Reinforcement Learning Optimization |
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| Volume | 43 |
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