8-Bit NCL Asynchronous Multiplier based on Radix-4 Booth Algorithm
Multiplier is one of the key modules in signal processing circuit and processor, and its robustness is especially important in the complex environment. Due to the lack of robustness of single-rail logic, a Null Convention Logic (NCL) Multiplier based on the Radix-4 Booth 8-bit fast parallel structur...
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| Published in | IOP conference series. Materials Science and Engineering Vol. 914; no. 1; pp. 12024 - 12031 |
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| Main Authors | , , , , |
| Format | Journal Article |
| Language | English |
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Bristol
IOP Publishing
01.09.2020
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| ISSN | 1757-8981 1757-899X 1757-899X |
| DOI | 10.1088/1757-899X/914/1/012024 |
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| Abstract | Multiplier is one of the key modules in signal processing circuit and processor, and its robustness is especially important in the complex environment. Due to the lack of robustness of single-rail logic, a Null Convention Logic (NCL) Multiplier based on the Radix-4 Booth 8-bit fast parallel structure is proposed in this paper. The Radix-4 Booth algorithm reduces the number of partial products to lower the computing time, and the "sign generate" algorithm simplifies sign extension bitcomputation. In order to demonstrate the effectiveness of the proposed hardware implementation scheme, we implement an improved 8-bit NCL multiplier on vivado platform, the speed of which is 14% higher than that of the traditional Wallace NCL 8bit multiplier. |
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| AbstractList | Multiplier is one of the key modules in signal processing circuit and processor, and its robustness is especially important in the complex environment. Due to the lack of robustness of single-rail logic, a Null Convention Logic (NCL) Multiplier based on the Radix-4 Booth 8-bit fast parallel structure is proposed in this paper. The Radix-4 Booth algorithm reduces the number of partial products to lower the computing time, and the “sign generate” algorithm simplifies sign extension bitcomputation. In order to demonstrate the effectiveness of the proposed hardware implementation scheme, we implement an improved 8-bit NCL multiplier on vivado platform, the speed of which is 14% higher than that of the traditional Wallace NCL 8bit multiplier. |
| Author | He, Anping Cheng, Jie Deng, Weixiang Ni, Leibin Cheng, Wenxiang |
| Author_xml | – sequence: 1 givenname: Weixiang surname: Deng fullname: Deng, Weixiang email: heap@lzu.edu.cn organization: School of information Science and Engineering, Lanzhou University , China – sequence: 2 givenname: Wenxiang surname: Cheng fullname: Cheng, Wenxiang email: 594766943@qq.com organization: School of information Science and Engineering, Lanzhou University , China – sequence: 3 givenname: Jie surname: Cheng fullname: Cheng, Jie email: 363999029@qq.com organization: Data Center Technology Laboratory, Huawei Technologies Co., Ltd. , China – sequence: 4 givenname: Leibin surname: Ni fullname: Ni, Leibin email: chengjie8@huawei.com organization: Data Center Technology Laboratory, Huawei Technologies Co., Ltd. , China – sequence: 5 givenname: Anping surname: He fullname: He, Anping email: nileibin@huawei.com organization: School of information Science and Engineering, Lanzhou University , China |
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| Cites_doi | 10.1016/j.vlsi.2003.12.004 10.1109/MWSCAS.1992.271307 10.1093/qjmam/4.2.236 10.2200/S00202ED1V01Y200907DCS023 10.1016/j.mee.2006.02.012 |
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| References | Bandapati (MSE_914_1_012024bib1) 2007; 84 Joshi (MSE_914_1_012024bib14) 2007 Weinberger (MSE_914_1_012024bib12) 1981 He (MSE_914_1_012024bib6) 2018; 46 Macsorley (MSE_914_1_012024bib11) 1961; 49 Millar (MSE_914_1_012024bib9) 1992 Fant (MSE_914_1_012024bib3) 2002 S.C. Smith (MSE_914_1_012024bib2) 2004; 37 Smith (MSE_914_1_012024bib13) 2004; 37 Smith (MSE_914_1_012024bib15) 2004; 39 Xiaoping (MSE_914_1_012024bib8) 2007 Booth (MSE_914_1_012024bib4) 1951; 4 Wallace (MSE_914_1_012024bib5) 1964 Smith (MSE_914_1_012024bib10) 2009; 4 Ohkubo (MSE_914_1_012024bib7) 1995; 30 |
| References_xml | – volume: 37 start-page: 135 year: 2004 ident: MSE_914_1_012024bib2 article-title: Optimization of NULL convention self-timed circuits[J] publication-title: Integration the VLSI Journal doi: 10.1016/j.vlsi.2003.12.004 – volume: 49 start-page: 67 year: 1961 ident: MSE_914_1_012024bib11 article-title: High-speed arithmetic in binary computers[J] – start-page: 13 year: 1964 ident: MSE_914_1_012024bib5 article-title: A Suggestion for a Fast Multiplier[J] – volume: 46 start-page: 961 year: 2018 ident: MSE_914_1_012024bib6 article-title: Study of 8-bit Booth Asynchronous Multiplier based on two-phase handshake protocol with bounded bundle data[J] publication-title: Acta Electronica Sinica – start-page: 82 year: 2007 ident: MSE_914_1_012024bib8 article-title: 32 ×32 bit fast multiplier based on modified booth algorithm[J] – year: 1992 ident: MSE_914_1_012024bib9 article-title: A fast hybrid multiplier combining Booth and Wallace/Dadda algorithms[C] doi: 10.1109/MWSCAS.1992.271307 – volume: 4 start-page: 236 year: 1951 ident: MSE_914_1_012024bib4 article-title: signed binary multiplication technique [J] publication-title: Quarterly Journal of Mechanics and Applied Mathematics doi: 10.1093/qjmam/4.2.236 – year: 2002 ident: MSE_914_1_012024bib3 article-title: NULL Convention LogicTM: a complete and consistent logicfor asynchronous digital circuit synthesis[C] – volume: 4 start-page: 1 year: 2009 ident: MSE_914_1_012024bib10 article-title: Designing Asynchronous Circuits using NULL Convention Logic (NCL)[J] publication-title: Synthesis Lectures on Digital Circuits and Systems doi: 10.2200/S00202ED1V01Y200907DCS023 – year: 1981 ident: MSE_914_1_012024bib12 – volume: 30 start-page: 251 year: 1995 ident: MSE_914_1_012024bib7 publication-title: A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer[J] – volume: 37 start-page: 135 year: 2004 ident: MSE_914_1_012024bib13 article-title: Optimization of NULL convention self-timed circuits[J] publication-title: Integration the VLSI Journal doi: 10.1016/j.vlsi.2003.12.004 – volume: 84 start-page: 280 year: 2007 ident: MSE_914_1_012024bib1 article-title: Design and characterization of NULL convention arithmetic logic units[J] publication-title: Microelectronic Engineering doi: 10.1016/j.mee.2006.02.012 – year: 2007 ident: MSE_914_1_012024bib14 article-title: NCL Implementation of Dual-Rail 2S Complement 8Ã 8 Booth2 Multiplier using Static and Semi-Static Primitives[C] – volume: 39 year: 2004 ident: MSE_914_1_012024bib15 article-title: Development of a large word-width high-speed asynchronous multiply and accumulate unit[J] publication-title: Integration, the VLSI Journal |
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| SubjectTerms | Algorithms Circuits Computing time Microprocessors Null convention logic Robustness Signal processing |
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| Title | 8-Bit NCL Asynchronous Multiplier based on Radix-4 Booth Algorithm |
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