A novel semi-folded parallel successive cancellation-based polar decoder for optimal-register allocation

• Published in: The Journal of supercomputing Vol. 75; no. 11; pp. 7037 - 7052
• Main Authors: Indumathi, G., Aarthi, V. P. M. B., Ramesh, M.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.11.2019; Springer Nature B.V
• Subjects: Algorithms; Architecture; Cancellation; Coding; Communication; Compilers; Computation; Computer Science; Data compression; Data transmission; Decoding; Information retrieval; Information theory; Interpreters; Lookup tables; Mobile communication systems; Processor Architectures; Programming Languages; Redundancy; Register allocation; Resource utilization; Very large scale integration; Weight; Resource utilization; Very large-scale integration; Polar coder; Semi-folded; Successive cancellation
• ISSN: 0920-8542; 1573-0484
• DOI: 10.1007/s11227-018-2519-y

Efficient compression and reliable data transmission are the major areas in the information theory that governs various applications in mobile communication, Internets and modern digital technology. The exploitation of data patterns and redundancies offers better compression without loss of user information. The trade-off between the storage and the quality is the major requirement to apply the coding scheme in very large-scale integration. Alternatively, the reliable transmission in the presence of noise requires the prior addition of redundancy to the data. Polar codes are the practical codes suitable for channel coding and optimal performance achievement under lossy compression and complexity-based communication environment. This paper focuses on the novel architecture of successive cancellation (SC)-based polar decoding for an effective communication. The coefficient weight computation during the register update consumes a number of components in traditional SC decoding architectures. This paper proposes the semi-folded parallel successive cancellation (SFPSC) algorithm that modifies the coefficient weight computation process for register update resulting in a 4-folded polar decoding architecture to retrieve the information from the transmitted symbols with reduced resource utilization. The performance characteristics of SFPSC algorithm based on FPGA implementation are presented. The decoder architecture based on SFPSC algorithm achieves an efficient resource utilization. The reduction in a number of components efficiently reduces the time consumption. The comparative analysis between the SFPSC-based decoder with the existing SC schemes regarding the number of look up tables, FFs and memory assures the effectiveness of SFPSC in resource utilization.