Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip

• Published in: Journal of circuits, systems, and computers Vol. 33; no. 12
• Main Authors: Kunthara, Rose George, James, Rekha K., Sleeba, Simi Zerine, Jose, John
• Format: Journal Article
• Language: English
• Published: Singapore World Scientific Publishing Company 01.08.2024; World Scientific Publishing Co. Pte., Ltd
• Subjects: Buffers; Communications traffic; Deflection; Energy dissipation; Multiprocessing; Network latency; Performance enhancement; Power efficiency; Power management; Routers; System on chip; deflection rate; throughput; CMesh; average latency; Network-on-Chip; bufferless router
• ISSN: 0218-1266; 1793-6454
• DOI: 10.1142/S0218126624502074

On-chip interconnection networks are primarily designed for efficient, high-performance Tiled Chip Multi-Processors (TCMP) architectures. Bufferless Network-on-Chip (NoC) is a better design option owing to their simpler router structure, area and power efficiency. Deflection routers have similar network performance of buffered designs at low to medium network traffic as deflections are minimal. But when network load increases, deflections also rise rapidly leading to poor network performance because of increased latency, power dissipation and unbalanced traffic. In this work, we propose a subnetwork based adaptive Concentrated Mesh (CMesh) bufferless router where deflections are considerably reduced by redirecting competing flit in one subnetwork to vacant port of the other subnetwork without any additional cycle latency. Simulations conducted over two-dimensional and multidimensional CMesh networks show that our topologically independent, adaptive deflection routing mechanism provides better network load balance and improves performance by minimizing unbounded deflections when compared to designs under consideration.