Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 34; no. 7; pp. 1082 - 1095
• Main Authors: Hills, Gage, Jie Zhang, Shulaker, Max Marcel, Hai Wei, Chi-Shuen Lee, Balasingam, Arjun, Wong, H.-S Philip, Mitra, Subhasish
• Format: Journal Article
• Language: English
• Published: IEEE 01.07.2015
• Subjects: Carbon Nanotube; Carbon Nanotube Variations; Circuit synthesis; CNTFETs; Computational modeling; Delay Optimization; Delays; Design-Technology Co-optimization; Integrated circuit modeling; Logic gates; Noise; delay optimization; Carbon nanotube (CNT); CNT variations; design-technology co-optimization
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2015.2415492

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over 100× faster than existing approaches and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with ≤5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints.