A Cryogenic 10-bit Successive Approximation Register Analog-to-Digital Converter Design with Modified Device Model

A 10-bit 500 kHz low-power successive approximation register（SAR）analog-to-digital converter（ADC）for cryogenic infrared readout circuit is proposed.To improve the simulation accuracy of metal-oxidesemiconductor field-efect transistors（MOSFETs）,corresponding modification in device model is presented...

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Published inShanghai jiao tong da xue xue bao Vol. 18; no. 5; pp. 520 - 525
Main Author 赵毅强 杨明 赵宏亮
Format Journal Article
LanguageEnglish
Published Berlin/Heidelberg Springer Berlin Heidelberg 01.10.2013
Subjects
Analog to digital conversion
Architecture
Circuits
Computer Science
Converters
Devices
Electrical Engineering
Engineering
Life Sciences
Materials Science
Mathematical analysis
MOSFETs
Registers
Synthetic aperture radar
comparator
device model
TN 432
parameter extraction
cryogenic
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ISSN1007-1172
1995-8188
DOI10.1007/s12204-013-1436-8

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Summary:A 10-bit 500 kHz low-power successive approximation register（SAR）analog-to-digital converter（ADC）for cryogenic infrared readout circuit is proposed.To improve the simulation accuracy of metal-oxidesemiconductor field-efect transistors（MOSFETs）,corresponding modification in device model is presented on the basis of BSIM3v3 with parameter extraction at 77 K.Corresponding timing is adopted in comparator to eliminate the influence caused by abnormal performance of MOSFETs at 77 K.The SAR ADC is fabricated and verified by standard 0.35μm complementary metal oxide semiconductor（CMOS）process.At 77 K,measurement results show that signal to noise and distortion ratio（SNDR）is 54.74 dB and efective number of bits（ENOB）is 8.8 at the sampling rate of 500 kHz.The total circuit consumes 0.6 mW at 3.3 V power supply.
Bibliography:cryogenic device model parameter extraction comparator
31-1943/U
A 10-bit 500 kHz low-power successive approximation register（SAR）analog-to-digital converter（ADC）for cryogenic infrared readout circuit is proposed.To improve the simulation accuracy of metal-oxidesemiconductor field-efect transistors（MOSFETs）,corresponding modification in device model is presented on the basis of BSIM3v3 with parameter extraction at 77 K.Corresponding timing is adopted in comparator to eliminate the influence caused by abnormal performance of MOSFETs at 77 K.The SAR ADC is fabricated and verified by standard 0.35μm complementary metal oxide semiconductor（CMOS）process.At 77 K,measurement results show that signal to noise and distortion ratio（SNDR）is 54.74 dB and efective number of bits（ENOB）is 8.8 at the sampling rate of 500 kHz.The total circuit consumes 0.6 mW at 3.3 V power supply.
ZHAO Yi-qiang1., YANG Ming1 ZHAO Hong-liang（1. School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China 2. College of Physics, Liaoning University, Shenyang 110036, China）
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ISSN:1007-1172
1995-8188
DOI:10.1007/s12204-013-1436-8