A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology
A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate（AG） and b...
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| Published in | Chinese physics B Vol. 25; no. 2; pp. 436 - 440 |
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| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
01.02.2016
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1674-1056 2058-3834 1741-4199 |
| DOI | 10.1088/1674-1056/25/2/027306 |
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| Summary: | A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate（AG） and back-side etching（BE）. The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping（VLD） and the ＂hot-spot＂ caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V. |
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| Bibliography: | Yan-Hui Zhang, Jie Wei, Chao Yin, Qiao Tan, Jian-Ping Liu, Peng-Cbeng Li, and Xiao-Rong Luo State Key Laboratory of ElectroniC2scienceThinandFilmsTechnology,vand Integratedan al..Devices＇r University of Electronic Science and Technology of China, Chengdu 610054, China LDMOS, accumulation gate, back-side etching, breakdown voltage, specific on-resistance A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate（AG） and back-side etching（BE）. The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping（VLD） and the ＂hot-spot＂ caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V. 11-5639/O4 ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
| ISSN: | 1674-1056 2058-3834 1741-4199 |
| DOI: | 10.1088/1674-1056/25/2/027306 |