A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors

• Published in: Journal of semiconductors Vol. 33; no. 6; pp. 51 - 55
• Main Author: 周凯敏 王自强 张春 王志华
• Format: Journal Article
• Language: English
• Published: 01.06.2012
• Subjects: PF; Verilog-A; 免疫; 对称; 电容式传感器; 读出电路; 运算放大器; 高线性
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/33/6/065001

A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch,a symmetrical readout circuit is realized.The linear input range is increased, and the systematic offsets of two input op-amps are cancelled.The common-mode noise and even-order distortion are also rejected.A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps,and a Verilog-A-based varactor is used to model the real variable sensing capacitor.Simulation results show that the output voltage of this proposed readout circuit responds correctly,while the under-test capacitance changes with a frequency of 1 kHz.A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF,linearity error below 1%and power consumption as low as 2.5 mW.This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.