CMOS implementation of a low-power BPSK demodulator for wireless implantable neural command transmission
A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower po...
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Published in | Journal of semiconductors Vol. 33; no. 5; pp. 113 - 119 |
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Main Author | |
Format | Journal Article |
Language | English |
Published |
01.05.2012
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Subjects | |
Online Access | Get full text |
ISSN | 1674-4926 |
DOI | 10.1088/1674-4926/33/5/055005 |
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Summary: | A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system.The proposed BPSK demodulator was implemented by Global Foundries 0.35μm CMOS technology with a 3.3 V power supply.The designed chip area is only 0.07 mm~2 and the power consumption is 0.5 mW.The test results show that it can work correctly. |
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Bibliography: | Wu Zhaohui, Zhang Xu, Liang Zhiming, and Li Bin(1 Institute of Microelectronics, School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510640, China 2State Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China) A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system.The proposed BPSK demodulator was implemented by Global Foundries 0.35μm CMOS technology with a 3.3 V power supply.The designed chip area is only 0.07 mm~2 and the power consumption is 0.5 mW.The test results show that it can work correctly. CMOS integrated circuits low-power BPSK demodulator implantable biomedical devices wireless command transmission 11-5781/TN ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
ISSN: | 1674-4926 |
DOI: | 10.1088/1674-4926/33/5/055005 |