Formation of stacked ruthenium nanocrystals embedded in SiO2 for nonvolatile memory applications

Two methods are proposed to fabricate stacked ruthenium (Ru) nanocrystals (NCs): rapid thermal annealing (RTA) for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×1...

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Bibliographic Details
Published inJournal of semiconductors Vol. 30; no. 9; pp. 9 - 12
Main Author 毛平 张志刚 潘立阳 许军 陈培毅
Format Journal Article
LanguageEnglish
Published IOP Publishing 01.09.2009
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ISSN1674-4926
DOI10.1088/1674-4926/30/9/093003

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Summary:Two methods are proposed to fabricate stacked ruthenium (Ru) nanocrystals (NCs): rapid thermal annealing (RTA) for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×10^12 cm^-2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor (MOS) capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.
Bibliography:stacked
TP333
TQ127.2
ruthenium nanocrystal; stacked; formation; nonvolatile memory
ruthenium nanocrystal
formation
11-5781/TN
nonvolatile memory
ISSN:1674-4926
DOI:10.1088/1674-4926/30/9/093003