A 2.4 GHz ultra-low power low-IF receiver and MUX-based transmitter for WPAN applications

This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consump...

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Bibliographic Details
Published inJournal of semiconductors Vol. 35; no. 6; pp. 90 - 95
Main Author 陈晶晶 刘威扬 刘晓东 张钊 刘力源 王海永 吴南健
Format Journal Article
LanguageEnglish
Published 01.06.2014
Subjects
CMOS
CMOS技术
GHz
Noise levels
Receivers
Receiving
Semiconductors
Transceivers
Transmission
Transmitters
Wireless communication
WPAN
低中频
变送器
接收器
无线个人区域网
超低功耗
Online AccessGet full text
ISSN1674-4926
DOI10.1088/1674-4926/35/6/065001

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Summary:This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consumption, an inductor- less receiver front-end, an adaptive analog baseband, a low power MUX and a current-reused phase-locked loop （PLL） have been proposed in this work. Measured results show that the receiver achieves-8 dBrn of lIP3 and 31 dB of image rejection. The transmitter delivers 0 dBm output power at a data rate of 2 Mbps. The current consumption is 7.2 mA in the receiving mode and 6.9 mA in the transmitting mode, respectively.
Bibliography:CMOS; low power; low-IF; MUX; RF transceiver; WPAN
11-5781/TN
This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consumption, an inductor- less receiver front-end, an adaptive analog baseband, a low power MUX and a current-reused phase-locked loop （PLL） have been proposed in this work. Measured results show that the receiver achieves-8 dBrn of lIP3 and 31 dB of image rejection. The transmitter delivers 0 dBm output power at a data rate of 2 Mbps. The current consumption is 7.2 mA in the receiving mode and 6.9 mA in the transmitting mode, respectively.
Chen Jinjing, Liu Weiyang, Liu Xiaodong, Zhang Zhao, Liu Liyuan, Wang Haiyong, Wu Nanjian State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China
ObjectType-Article-1
SourceType-Scholarly Journals-1
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ISSN:1674-4926
DOI:10.1088/1674-4926/35/6/065001