Analytical model for high-voltage SOI device with composite-k dielectric buried layer
An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction....
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| Published in | Journal of semiconductors Vol. 34; no. 9; pp. 67 - 72 |
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| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
01.09.2013
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1674-4926 |
| DOI | 10.1088/1674-4926/34/9/094008 |
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| Abstract | An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage （BV） is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional （2-D） potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 （LK SOl）, simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively. |
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| AbstractList | An analytical model for a novel high voltage silicon-on-insulator device with composite-k (relative permittivity) dielectric buried layer (CK SOI) is proposed. In this structure, the composite-k buried layer is composed by alternating Si sub(3)N sub(4) and low-k (k = 2.65) dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage (BV) is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si sub(3)N sub(4) buried layer and investigated the modulation effect of accumulated holes on the two-dimensional (2-D) potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SOI (LK SOI), simulation results show that the BV for CK SOI is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively. An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage （BV） is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional （2-D） potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 （LK SOl）, simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively. |
| Author | 范杰 张波 罗小蓉 汪志刚 李肇基 |
| AuthorAffiliation | State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technologyof China, Chengdu 610054, China |
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| Cites_doi | 10.1109/16.841233 10.1088/1674-4926/33/7/074005 10.1016/S0038-1101(03)00222-3 10.1109/TED.2009.2028405 10.1109/TED.2009.2037372 10.1016/S0040-6090(98)01186-9 10.1007/s003390000562 10.1016/j.sse.2011.12.010 10.1088/1674-4926/33/10/104003 10.1109/16.760414 10.1088/1674-4926/31/8/084012 10.1016/S0038-1101(00)00271-9 10.1109/16.777174 10.1016/j.mejo.2006.03.004 10.1088/0268-1242/26/11/115002 10.1109/LED.2010.2046616 10.1016/j.sse.2007.01.034 |
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| Notes | Fan Jie, Zhang Bo, Luo Xiaorong Wang Zhigang, and Li Zhaoji State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China composite-k dielectric; accumulated holes; potential well; electric field; SOI 11-5781/TN An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage （BV） is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional （2-D） potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 （LK SOl）, simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively. ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
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| References | Merchant S (3) 1991 13 14 15 17 Luo X (19) 2010; 31 18 Nakagawa A (2) 1992 Zhu R (5) 2010 1 Darbandy G (6) 2011; 26 Luo Xiaorong (12) 2012; 33 4 Ge Rui (11) 2012; 33 7 8 9 Guo Yufeng (16) 2004; 25 Gao Huanmei (10) 2010; 31 20 21 |
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| SubjectTerms | Computer simulation Devices Dielectrics Electric potential Mathematical analysis Modulation Semiconductors Silicon nitride SOI器件 仿真结果 低k电介质 埋层 复合介电常数 模型开发 模型显示 高电压 |
| Title | Analytical model for high-voltage SOI device with composite-k dielectric buried layer |
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