Analytical model for high-voltage SOI device with composite-k dielectric buried layer

An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction....

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Bibliographic Details
Published inJournal of semiconductors Vol. 34; no. 9; pp. 67 - 72
Main Author 范杰 张波 罗小蓉 汪志刚 李肇基
Format Journal Article
LanguageEnglish
Published 01.09.2013
Subjects
Computer simulation
Devices
Dielectrics
Electric potential
Mathematical analysis
Modulation
Semiconductors
Silicon nitride
SOI器件
仿真结果
低k电介质
埋层
复合介电常数
模型开发
模型显示
高电压
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ISSN1674-4926
DOI10.1088/1674-4926/34/9/094008

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Summary:An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage （BV） is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional （2-D） potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 （LK SOl）, simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.
Bibliography:Fan Jie, Zhang Bo, Luo Xiaorong Wang Zhigang, and Li Zhaoji State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
composite-k dielectric; accumulated holes; potential well; electric field; SOI
11-5781/TN
An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage （BV） is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional （2-D） potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 （LK SOl）, simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.
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ISSN:1674-4926
DOI:10.1088/1674-4926/34/9/094008