A comprehensive analysis of reduced switch count multilevel inverter
Multilevel inverters (MLIs) have been recognised to generate the voltage for power quality applications. Presently number of topological improvements have been reported in literature. In higher level stages, it requires increased number of semiconductor devices that make the topology more complex, i...
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| Published in | Australian journal of electrical & electronics engineering Vol. 17; no. 1; pp. 13 - 27 |
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| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
Taylor & Francis
02.01.2020
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1448-837X 2205-362X |
| DOI | 10.1080/1448837X.2019.1693884 |
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| Summary: | Multilevel inverters (MLIs) have been recognised to generate the voltage for power quality applications. Presently number of topological improvements have been reported in literature. In higher level stages, it requires increased number of semiconductor devices that make the topology more complex, increases the cost and reduced the reliability of system. Paper discusses the method to reduce the number of switches for increased level of MLIs. It is evident from literature that RSC-MLIs, reduces the requirement of gate circuits, reduction in size and improves the power quality. It has multiple configurations based on topology and control structures. In this study, RSC-MLI configurations have been analysed. Modified selective harmonic elimination technique has been presented to control the magnitude of input DC-link and optimal switching angles. |
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| ISSN: | 1448-837X 2205-362X |
| DOI: | 10.1080/1448837X.2019.1693884 |