A high-pass shaped LMS algorithm based predistortion technique for fractional-N BB-DPLLs

In this paper, we prove that rather than the second-order ΔΣ modulator (DSM) as typically believed using the first-order one yields a faster convergence for the linear-piecewise predistortion technique employed in digital/time converter (DTC) based fractional-N Bang-Bang digital phase-locked-loops (...

Full description

Saved in:
Bibliographic Details
Published inMicroelectronics Vol. 146; p. 106153
Main Author Vo, Tuan Minh
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.04.2024
Subjects
Digital BB-PLL
Digital predistortion
Dtc
High-pass shaped
Multi-lms-loop
Piecewise-linear
Digital predistortion
Piecewise-linear
Dtc
Multi-lms-loop
Digital BB-PLL
High-pass shaped
Online AccessGet full text
ISSN1879-2391
DOI10.1016/j.mejo.2024.106153

Cover

More Information
Summary:In this paper, we prove that rather than the second-order ΔΣ modulator (DSM) as typically believed using the first-order one yields a faster convergence for the linear-piecewise predistortion technique employed in digital/time converter (DTC) based fractional-N Bang-Bang digital phase-locked-loops (BB-DPLLs). We also propose a novel technique that addresses the limit-cycle issue happening in near-integer channels of the conventional BB-DPLLs. With the first-order DSM-based novel technique, simulation results show that the worst fractional spurs are below −83 dBc at 12 kHz offset frequency assuming the DTC’s integral nonlinearity error is as large as 5 least-significant-bits.
ISSN:1879-2391
DOI:10.1016/j.mejo.2024.106153