SFD-resistant joint time-frequency symbol timing recovery algorithm and parallel FPGA implementation for broadband satellite communication

• Published in: Digital signal processing Vol. 160; p. 105051
• Main Authors: Zhang, Peixin, Li, Guo, Gong, Fengkui, Zhang, Nan, Wang, Daqing, Li, Zhao
• Format: Journal Article
• Language: English
• Published: Elsevier Inc 01.05.2025
• Subjects: Frequency-domain estimation; Parallel FPGA; Symbol timing recovery (STR); Time-domain interpolation; Symbol timing recovery (STR); Frequency-domain estimation; Parallel FPGA; Time-domain interpolation
• ISSN: 1051-2004
• DOI: 10.1016/j.dsp.2025.105051

Existing symbol timing recovery (STR) algorithms face challenges in achieving a delicate balance between high throughput, high convergence accuracy, and robust resistance to sampling frequency deviation (SFD) while maintaining low complexity. For ultra-wideband single-carrier communication systems especially in the field of satellite communication (SatCom), we propose a joint time-frequency algorithm for multi-rate and SFD-resistant STR with low complexity. Additionally, we optimize the frequency-domain (FD) Barton estimator to enhance overall performance of the system. Simultaneously, the joint algorithm of the time-domain (TD) interpolation and the FD timing phase correction demonstrates increased resilience to more severe SFD. The corresponding field programmable gate array (FPGA) implementation is then realized, and the simulation results reveal a 2 dB reduction in mean square error and a 0.25 dB reduction in bit error rate loss compared to the original algorithm. The proposed algorithm can effectively resist SFD within ±2000 ppm (point per million). Through the FPGA verification based on the XCVU13P processor, the proposed algorithm achieves a bit throughput of 25.6 Gbit/s with 4.6% look-up tables and 6.1% digital signal processors, respectively.