PQPU: A 4.4-μJ/Op 69.4-kOPS Agile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems

• Published in: IEEE journal of solid-state circuits Vol. 60; no. 6; pp. 2261 - 2275
• Main Authors: Zhu, Yihong, Zhu, Wenping, Ouyang, Yi, Sun, Junwen, Zhao, Qi, Zhu, Min, Yang, Jinjiang, Chen, Chen, Tao, Qichao, Wang, Hanning, Yang, Guang, Wei, Shaojun, Zhang, Aoyang, Liu, Leibo
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Clustering; Clustering algorithms; Computer architecture; Cryptography; Cryptography processor; Energy efficiency; Field programmable gate arrays; Hardware; high throughput; Mathematical problems; Microprocessors; NIST; Parallel processing; post-quantum cryptography (PQC); Quantum computing; Quantum cryptography; reconfigurable architecture; Standardization; Throughput
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2024.3476949

Post-quantum cryptography (PQC) is currently being standardized to replace the existing public-key cryptography for data security in the era of quantum computing. PQC algorithms exhibit considerable diversity in their underlying mathematical problems, storage requirements, and computational patterns, thus complicating unified PQC architecture design. To address this issue, a unified PQC domain-specific accelerator (DSA), post-quantum processing unit (PQPU), is proposed to address the trade-off between performance and flexibility at the algorithm, architecture, and circuit levels. First, a task-clustering-based framework is proposed to enable task-level parallel execution by utilizing the inherent parallelism and common functions across different PQC algorithms. Second, a region-based dynamically updated task path (TP) is constructed to facilitate automatic task-dependency management, with agile control flow and minimized overheads. Finally, algorithm-hardware co-optimizations are proposed in each task cluster to improve throughput and energy efficiency. Fabricated in a 28-nm process, PQPU has energy efficiency and throughput of <inline-formula> <tex-math notation="LaTeX">4.4~{\mu } </tex-math></inline-formula>J/Op and 69.4 kOPS. The energy-delay product (EDP) and throughput achieved are 19.3% and 44.6% compared to the state-of-the-art design, respectively. To the best of our knowledge, PQPU is the first silicon-proven PQC accelerator that supports all valid schemes in NIST PQC standardization.