Statistical Modelling of MOS Transistor Mismatch for High-voltage CMOS Processes

• Published in: Quality and reliability engineering international Vol. 21; no. 5; pp. 477 - 489
• Main Authors: Posch, Werner, Enichlmair, Hubert, Schirgi, Eduard, Rappitsch, Gerhard
• Format: Journal Article
• Language: English
• Published: Chichester, UK John Wiley & Sons, Ltd 01.08.2005
• Subjects: electronic circuits; high-voltage CMOS process; mismatch modeling; Monte Carlo simulation; MOS transistor; parameter extraction
• ISSN: 0748-8017; 1099-1638
• DOI: 10.1002/qre.735

The random mismatch of semiconductor devices caused by local variations of the production process strongly influences critical performance parameters of analog circuits. In order to estimate the influence of the device mismatch on the circuit yield during the design phase, statistical mismatch models for the individual components must be provided for circuit simulation. Based on extensive statistical measurements of matched pairs using special test structures, an algorithm is presented to extract device mismatch parameters for high‐voltage transistors. Due to the special construction of high‐voltage transistors the mismatch parameters must be determined in two steps taking into account the effect of the drift region at high gate voltages. Therefore, the device mismatch for the threshold voltage, the gain factor and the mobility reduction are extracted from a sensitivity model in saturation, whereas the extraction of the drift‐resistance mismatch uses a modified MOS transistor model in the ohmic region. Based on the mismatch parameters for several device sizes a proper geometric model is extracted allowing the mismatch parameters to be scaled with the device dimensions. The mismatch parameters are implemented as part of circuit simulation model libraries to be used for Monte Carlo simulation. Production control parameters enable the monitoring of device mismatch for high‐voltage CMOS transistors. Copyright © 2005 John Wiley & Sons, Ltd.