Low-latency Hardware Architecture for VDF Evaluation in Class Groups

• Published in: IEEE transactions on computers Vol. 72; no. 6; pp. 1706 - 1717
• Main Authors: Zhu, Danyang, Tian, Jing, Li, Minghao, Wang, Zhongfeng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: ASIC; blockchain; Blockchains; class groups; Computer architecture; Cryptography; Delays; extended GCD; Hardware; Low latency communication; low-latency; Security; Software algorithms; verifiable delay functions
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2022.3219723

The verifiable delay function (VDF), as a kind of cryptographic primitives, has recently been adopted quite often in decentralized systems. Highly correlated to the security of VDFs, the fastest implementation for VDF evaluation is generally desired to be publicly known. In this paper, for the first time, we propose a low-latency hardware implementation for the complete VDF evaluation in the class group by jointly exploiting optimizations. On one side, we reduce the required computational cycles by decreasing the hardware-unfriendly divisions and increase the parallelism of computations by reducing the data dependency. On the other side, we provide low-latency large-number divisors, multipliers, and adders, respectively, while those operators are generally very hard to be accelerated. Besides, we carefully schedule the sub-modules and devise the low-latency architecture for the complete VDF evaluation. Finally, the proposed design is coded and synthesized under the TSMC 28-nm CMOS technology. The experimental results show that our design can achieve a speedup of 3.5x compared to the optimal C++ implementation for the VDF evaluation over an advanced CPU. Moreover, compared to the state-of-the-art hardware implementation for the squaring, a key step of VDF, we achieve about 2x speedup.