An Optimized VLSI Implementation of the Least Mean Square (LMS) Adaptive Filter Architecture on the Basis of Distributed Arithmetic Approach

• Published in: Journal of the Institution of Engineers (India). Series B, Electrical Engineering, Electronics and telecommunication engineering, Computer engineering Vol. 106; no. 3; pp. 861 - 870
• Main Authors: Nagabushanam, M., Chakrasali, Sadashiva, Gangadharaiah, S. L., Patel, Sampath H., Ramaiah, Gurumurthy, Basak, Raju
• Format: Journal Article
• Language: English
• Published: New Delhi Springer India 01.06.2025; Springer Nature B.V
• Subjects: Adaptive filters; Algorithms; Arithmetic; Beamforming; Binary codes; Communications Engineering; Complexity; Computer architecture; Criteria; Design; Engineering; Field programmable gate arrays; FIR filters; Image coding; Large scale integration; Linear prediction; Mathematical analysis; Mean square values; Memory; Multiplication & division; Networks; Original Contribution; Performance enhancement; Power consumption; Very large scale integration; Adaptive FIR Filters; Distributed Arithmetic; Pipeline Architecture; Least Mean Square
• ISSN: 2250-2106; 2250-2114
• DOI: 10.1007/s40031-024-01028-9

Adaptive filters find applications in many areas such as echo cancellation in long-distance telephone networks, linear prediction of the signal in speech and image coding, channel equalization, beam forming and many more. In adaptive filters, the time-varying coefficients can be determined based on different criterion; in the proposed work, least mean square (LMS) error criterion is used to implement in very-large-scale integration. Less-complexity LMS filters use less power, but as computation speed and the quantity of functional units per unit area rise, more power is lost. The utilization of offset binary coding (OBC) combinations for input samples in hardware implementation has led to a reduction in the complexity of the suggested architectures. However, some non-OBC outputs are generated and then eliminated during the initial clock cycles when calculating errors. The Radix 4 OBC combinations of the input samples are combined with the proposed partial product generators in order to further improve the performance of the proposed algorithm. New straightforward versions of the weight update block, offset term, and shift-accumulate unit are proposed. Optimal tuning of the least mean square (LMS) algorithm enables a trade-off between speed and power consumption. This permits either a controlled reduction in speed with lowered power usage or a heightened speed while maintaining limited power consumption. Notably, the use of pipelines successfully shortens the critical path. Throughput performance can be improved by using delayed LMS (DLMS), a pipelined variation of LMS. The effective implementation of FIR filters uses distributed arithmetic (DA), a popular multiplier-less technique is proposed which optimizes area and power consumed by the architecture, and the performance is better than that proposed in the literature.