A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self- locking comparators
This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditi...
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| Published in | Journal of semiconductors Vol. 36; no. 5; pp. 144 - 150 |
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| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
01.05.2015
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1674-4926 |
| DOI | 10.1088/1674-4926/36/5/055009 |
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| Abstract | This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of dis- tributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to- noise plus distortion ratio （SNDR） is 32.13 dB and the spurious-free dynamic range （SFDR） is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step. |
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| AbstractList | This paper presents a 6-b successive approximation register (SAR) ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of distributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to-noise plus distortion ratio (SNDR) is 32.13 dB and the spurious-free dynamic range (SFDR) is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm super(2) and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step. This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of dis- tributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to- noise plus distortion ratio （SNDR） is 32.13 dB and the spurious-free dynamic range （SFDR） is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step. |
| Author | 向济璇 陈迟晓 叶凡 许俊 李宁 任俊彦 |
| AuthorAffiliation | State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China |
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| Cites_doi | 10.1109/TCSI.2012.2215756 10.1109/JSSC.2008.2006315 10.1109/JSSC.2010.2042254 10.1109/JSSC.2012.2214181 10.1109/JSSC.2007.892169 10.1109/JSSC.2013.2279419 10.1109/JSSC.2006.884231 10.1109/JSSC.2012.2204543 10.1109/JSSC.2008.2012329 |
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| DocumentTitleAlternate | A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self- locking comparators |
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| Notes | Xiang Jixuan, Chen Chixiao, Ye Fan, Xu Jun, Li Ning, and Ren Junyan State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China SAR ADC; high speed; 2-b/stage; new switching procedure; self-locking 11-5781/TN This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of dis- tributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to- noise plus distortion ratio （SNDR） is 32.13 dB and the spurious-free dynamic range （SFDR） is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step. ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
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| References | 11 12 13 Hong H K (9) Xue Han (15) 2014; 35 Yang J (14) Ma J X (1) Lien Y C (8) 2 3 4 Wong S S (5) 6 7 10 |
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| Snippet | This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this... This paper presents a 6-b successive approximation register (SAR) ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this... |
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| SubjectTerms | ADC CMOS工艺 Comparators Electric potential Figure of merit Mathematical analysis Noise levels Sampling SAR Semiconductors Switching 交换过程 内置 自锁 舞台 |
| Title | A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self- locking comparators |
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