A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self- locking comparators

This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditi...

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Bibliographic Details
Published inJournal of semiconductors Vol. 36; no. 5; pp. 144 - 150
Main Author 向济璇 陈迟晓 叶凡 许俊 李宁 任俊彦
Format Journal Article
LanguageEnglish
Published 01.05.2015
Subjects
ADC
CMOS工艺
Comparators
Electric potential
Figure of merit
Mathematical analysis
Noise levels
Sampling
SAR
Semiconductors
Switching
交换过程
内置
自锁
舞台
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ISSN1674-4926
DOI10.1088/1674-4926/36/5/055009

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Summary:This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of dis- tributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to- noise plus distortion ratio （SNDR） is 32.13 dB and the spurious-free dynamic range （SFDR） is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step.
Bibliography:Xiang Jixuan, Chen Chixiao, Ye Fan, Xu Jun, Li Ning, and Ren Junyan State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
SAR ADC; high speed; 2-b/stage; new switching procedure; self-locking
11-5781/TN
This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of dis- tributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to- noise plus distortion ratio （SNDR） is 32.13 dB and the spurious-free dynamic range （SFDR） is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step.
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ISSN:1674-4926
DOI:10.1088/1674-4926/36/5/055009