Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decrease...

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Bibliographic Details
Published inChinese physics B Vol. 26; no. 8; pp. 407 - 410
Main Author 王艳蓉 杨红 徐昊 罗维春 祁路伟 张淑祥 王文武 闫江 朱慧珑 赵超 陈大鹏 叶甜春
Format Journal Article
LanguageEnglish
Published 01.08.2017
Subjects
PMOS
制备过程
多段
应力诱导
电流特性
等效氧化层厚度
退火工艺
退火时间
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ISSN1674-1056
2058-3834
DOI10.1088/1674-1056/26/8/087304

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Summary:In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decreases when the annealing time（s） change from 1 to 2. Furthermore, the characteristics of SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time（s） from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.
Bibliography:high-k/metal gate, multi deposition multi annealing, stress-induced leakage current, post deposi-tion annealing
In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decreases when the annealing time（s） change from 1 to 2. Furthermore, the characteristics of SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time（s） from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.
11-5639/O4
Yanrong Wang1,2,3, Hong Yang1,3, Hao Xu1,3, Weichun Luo1,3, Luwei Qi1,3, Shuxiang Zhang1,3, Wenwu Wang1,3, Jiang Yan2,Huilong Zhu1,3, Chao Zhao1,3, Dapeng Chen1,3, and Tianchun Ye1,3（1 Key Laboratory of Microelectronics Devices ＆ Integrated Technology, Institute of MicroElectronics, Chinese Academy of Sciences, Beijing 100029, China 2North China University of Technology, Beijing 100144, China 3 University of Chinese Academy of Sciences, Beijing 100049, China）
ISSN:1674-1056
2058-3834
DOI:10.1088/1674-1056/26/8/087304