SIGMA: a VLSI systolic array implementation of a Galois field GF(2/sup m/) based multiplication and division algorithm

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. A new algorithm based on a pattern ma...

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Bibliographic Details
Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 1; no. 1; pp. 22 - 30
Main Authors Kovac, M., Ranganathan, N., Varanasi, M.
Format Journal Article
LanguageEnglish
Published IEEE 01.03.1993
Subjects
CMOS technology
Computer architecture
Cryptography
Design methodology
Digital signal processing
Error correction codes
Galois fields
Signal processing algorithms
Systolic arrays
Very large scale integration
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ISSN1063-8210
DOI10.1109/92.219904

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Summary:Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. A new algorithm based on a pattern matching technique for computing multiplication and division in GF(2/sup m/) is presented. An efficient systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle and the multiplication and division operations can be interleaved. The architecture has been implemented using 2- mu m CMOS technology. The chip yields a computational rate of 33.3 million multiplications/divisions per second.< >
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ISSN:1063-8210
DOI:10.1109/92.219904