Implementation of Polyphase Digital Down Converter Using Optimized LMS Algorithm for WCDMA Application

• Published in: IEEE embedded systems letters Vol. 16; no. 4; pp. 533 - 536
• Main Authors: Datta, Debarshi, Naskar, Mrinal Kanti
• Format: Journal Article
• Language: English
• Published: IEEE 01.12.2024
• Subjects: Adaptive filters; Computer architecture; Convergence; Digital down converter (DDC); Dynamic range; Field programmable gate arrays; field-programmable gate array (FPGA); Filtering; Hardware; least mean square (LMS); Multiaccess communication; Particle swarm optimization; particle swarm optimization (PSO); Spread spectrum communication; spurious-free dynamic range (SFDR)
• ISSN: 1943-0663; 1943-0671
• DOI: 10.1109/LES.2024.3473539

This letter presents the implementation of a polyphase digital down converter (DDC) that employs a least mean square (LMS) algorithm associated with particle swarm optimization (PSO) for the wideband code division multiple access (WCDMA) application. The PSO-based LMS algorithm suppresses the noise signal, enabling a significant improvement in the spurious-free dynamic range (SFDR), which is 130 dB. The complex multiplication is realized by the canonical impel-mentation to reduce the number of multipliers. The suggested polyphase DDC architecture is successfully implemented in the field-programmable gate array device (FPGA) Kintex-7 platform. To achieve high accuracy, the proposed design is implemented with an efficient user-defined floating-point representation data type. Synthesis results suggested that the design consumes less area and power compared to the most recent structure.