Iterative computing algorithms implemented in FPGA using ALTERA_CORDIC library as an example

• Published in: Procedia computer science Vol. 246; pp. 2380 - 2389
• Main Author: Poczekajło, Paweł
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 2024
• Subjects: Altera; computing algorithms; CORDIC; engineering computing; finite precision; FPGA; frequency; implementation; iterative algorithms; library; occupation; pipelined algorithms; library; occupation; computing algorithms; FPGA; finite precision; implementation; engineering computing; Altera; pipelined algorithms; CORDIC; iterative algorithms; frequency
• ISSN: 1877-0509; 1877-0509
• DOI: 10.1016/j.procs.2024.09.533

The article discusses the general issues of implementing pipelined and iterative algorithms. These are typical solutions for engineering algorithms implemented in hardware like reprogrammable systems. The authors focused on the implementation of such algorithms in field-programmable gate array (FPGA) circuits. Key aspects and advantages of pipelined processing were discussed. The focus was on an example CORDIC algorithm. Analyses of the iterative implementation using the ALTERA_CORDIC library were performed. Key parameters such as frequency and circuit occupancy were measured. Also, the obtained results were compared with the exact values - the errors were determined. Realizations based on 8-, 12- and 16-bits of fractional in fixed-position notation were analyzed.