Recursive least-square algorithm with ud factorization by fixed-point arithmetic
It is known that a recursive least‐square (RLS) algorithm with UD factorization equivalent to the (standard) RLS algorithm can be realized by using the systolic array proposed by Kung. In general, in constructing a special hardware, the wordlength of a processor is related to the arithmetic processi...
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| Published in | Electronics & communications in Japan. Part 3, Fundamental electronic science Vol. 75; no. 1; pp. 42 - 52 |
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| Main Authors | , , |
| Format | Journal Article |
| Language | English |
| Published |
New York
Wiley Subscription Services, Inc., A Wiley Company
01.01.1992
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1042-0967 1520-6440 |
| DOI | 10.1002/ecjc.4430750105 |
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| Summary: | It is known that a recursive least‐square (RLS) algorithm with UD factorization equivalent to the (standard) RLS algorithm can be realized by using the systolic array proposed by Kung. In general, in constructing a special hardware, the wordlength of a processor is related to the arithmetic processing speed and the area of the hardware. Therefore, an important subject is how to shorten the wordlength of processors used in the systolic array executing the RLS method with UD factorization.
The authors have already carried out an operational error analysis in finite wordlength floating‐point arithmetic and described that this algorithm can be executed with short arithmetic wordlength. If the algorithm can be executed with short arithmetic wordlength also in the fixed‐point arithmetic, then we can expect improved operational processing speed and simpler hardware structure compared to the special hardware of the floating‐point arithmetic mode.
Thus, this paper describes an RLS method by finite wordlength fixed‐point arithmetic with UD factorization and evaluates the operational error. Then the evaluation of convergence values and number of updates of the algorithm are shown analytically. Finally, the appropriateness of theoretical analysis results of convergence values and the number of updates are confirmed by computer simulations. |
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| Bibliography: | ark:/67375/WNG-97FHKDZW-6 istex:A9D72C70573060EE4700C84D56D45ACBEA55E0FE ArticleID:ECJC4430750105 1958 from the Dept. of Electric Engineering, School of Science and Engineering, Tokyo Institute of Technology. He also has a Dr. of Sci. degree. He joined NEC in 1958. In 1965, he was appointed an Associate Professor at Yamanashi University, in 1971 an Associate Professor at Tokyo Institute of Technology, where in 1978 he was promoted to Professor. He is engaged in research on information systems, digital signal processing, and cryptology. His written works include Application of Digital Signal Processing and Optical Fiber Information Network LAN. 1975 from the Dept. of Electronics Engineering, School of Engineering, Yamanashi University, and obtained a Dr. of Sci. degree in 1981 from Tokyo Institute of Technology. The same year, he was appointed an Assistant Professor at Chiba Institute of Technology, where in 1982 he became a Lecturer and in 1986 an Associate Professor. He is engaged in research on designing digital filter and adaptive signal processing. He is the co‐author of Revised Electronic Circuit (Corona Publ. Co.) and Digital Signat Prdcessing (Ohm Publ. Co.). He is the cotranslator of Itfonnatioti New Media Terminology (Kyoritsu Publ.). He is a member of IEEE. 1986 from the Dept. of Electric Engineering, School of Engineering, Chiba Institute of Technology, and obtained a Master's degree in 1988 from Tokyo Institute of Technology, where he is presently in the second half of the doctoral program. He is engaged in research on digital signal processing. |
| ISSN: | 1042-0967 1520-6440 |
| DOI: | 10.1002/ecjc.4430750105 |