A Fast OPC Algorithm for IC Layout Based on 1-D Cells after Optimization of Gap Distribution

As VLSI technology scales down to 45nm process node, reliable printing becomes a persistent huge challenge to IC's manufacturability. The limitation of RETs now forces people to adopt a regular 1-D cell design methodology. A method of extending the line-ends and inserting dummies to optimize th...

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Bibliographic Details
Published inECS transactions Vol. 34; no. 1; pp. 215 - 221
Main Authors Lin, Bin, Xie, Chenlei, Shi, Zheng
Format Journal Article
LanguageEnglish
Published 01.01.2011
Online AccessGet full text
ISSN1938-5862
1938-6737
DOI10.1149/1.3567584

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Summary:As VLSI technology scales down to 45nm process node, reliable printing becomes a persistent huge challenge to IC's manufacturability. The limitation of RETs now forces people to adopt a regular 1-D cell design methodology. A method of extending the line-ends and inserting dummies to optimize the gap distribution, with which the layout based on 1-D cells could get better printability, has been proposed in recent studies. In this paper, we present a fast OPC algorithm for IC layout based on 1-D cells after the previously proposed optimization of gap distribution. With this algorithm, during the OPC process, the extended parts and dummies of the layout are excluded from correction to save run time, and only the functional parts of the layout will be corrected. Experimental results on 45 nm process show excellent efficiency of this algorithm.
ISSN:1938-5862
1938-6737
DOI:10.1149/1.3567584