FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 72; no. 3; pp. 1093 - 1104
• Main Authors: Van Assche, Jonah, Frenkel, Charlotte, Safa, Ali, Gielen, Georges
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Algorithms; Biomedical materials; Biomedical SoC; Clocks; Coding; Electrocardiography; Encoding; event-driven sensing; Integrated circuits; level-crossing sampling; Logic; Microprocessors; Network latency; Neural networks; Power demand; Power efficiency; Power management; Real time; Sensors; Signal classification; Signal processing; Signal resolution; spiking neural networks; System on chip; Training
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2024.3504264

Biomedical systems-on-chip (SoCs) for real-time monitoring of vital signs need to read out multiple recording channels in parallel and process them locally with low latency, at a low per-channel area and power consumption. To achieve this, event-driven SoCs that exploit the time-sparse nature of biosignals such as the electrocardiogram (ECG) have been proposed; they only process the signal when it shows activity. Such SoCs convert time-sparse biosignals into spike trains, on which spiking neural networks (SNNs) can perform event-driven signal classification. State-of-the-art event-driven SoCs, however, still suffer from poor area and power efficiency and use inflexible, hard-coded spike-encoding schemes. To improve on these challenges, this paper presents FREYA, an 8-channel event-driven SoC for end-to-end sensing of time-sparse biosignals. The proposed SoC consists of the following key contributions: 1) an 8-channel time-division-multiplexed level-crossing sampling (LCS) analog-to-spike converter (ASC) that encodes analog input signals into input spikes for an on-chip SNN; 2) an ASC spike-encoding algorithm that is fully programmable in resolution (4 to 8 bits) and conversion algorithm (offset and decay parameters); 3) an on-chip integrated, flexible SNN processor based on a programmable crossbar architecture, that allows for efficient event-driven processing, and that can be reconfigured towards multiple sensing applications; 4) a custom offline end-to-end training framework for the fast retraining of the spike-encoding algorithm and SNN architecture towards new applications or patient-dependent signal variations. A prototype IC has been fabricated in a 40nm CMOS technology. It has a per-channel active area of 0.023 mm2 (0.184 mm2 in total), a <inline-formula> <tex-math notation="LaTeX">7\times </tex-math></inline-formula> improvement over the state of the art. For the use case of ECG-based QRS-labeling, a detection accuracy of 98.67% is achieved, while the system consumes <inline-formula> <tex-math notation="LaTeX">20.8~\mu </tex-math></inline-formula>W per channel and achieves a latency of only 80 ms, thus paving the way for multi-channel, high-fidelity, event-driven SoCs in biomedical applications.