An efficient unused integrated circuits detection algorithm for parallel scan architecture

• Published in: International journal of electrical and computer engineering (Malacca, Malacca) Vol. 14; no. 1; p. 469
• Main Authors: Sathyanarayana, Rekha, Kanathur Ramaswamy, Nataraj, Srikantaswamy, Mallikarjunaswamy, Kanathur Ramaswamy, Rekha
• Format: Journal Article
• Language: English
• Published: 01.02.2024
• ISSN: 2088-8708; 2722-2578
• DOI: 10.11591/ijece.v14i1.pp469-478

In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm.