Boolean Technology Mapping Based on Logic Decomposition

• Published in: 16th Brazilian Symposium on Integrated Circuit Design (SBCCI 2003) p. 35
• Main Authors: Damiani, Maurizio, Selchenko, Andrei Y.
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 08.09.2003
• Series: ACM Conferences
• Subjects: Computing methodologies > Symbolic and algebraic manipulation > Symbolic and algebraic algorithms; Hardware > Integrated circuits > Logic circuits; Mathematics of computing > Discrete mathematics > Graph theory > Graph algorithms; Software and its engineering > Software notations and tools > General programming languages > Language types; Theory of computation > Design and analysis of algorithms
• ISBN: 076952009X; 9780769520094
• DOI: 10.5555/942808.943942

The decomposition tree of a logic function first appears in the work of Ashenhurst [1]. It is a canonical [1, 2], tree-like logic network representing the decomposition properties of that function. We present an algorithm for technology mapping based on the use of such trees for the representation of library elements. Decomposition information is also embedded in the representation of leaf-dags of the subject graph. Because library functions are represented by trees, this approach allows us to combine Boolean matching with ef.cient tree-based matching algorithms. In this way, Boolean matching can now be used not only for incremental optimization, but also for building the initial mapping "from scratch". Finally, we remark that bycombining this method with the one of Lehman et al. we are able to represent implicitly a search space of unprecedented size for a subject graph. The algorithm has been implemented in C++ in a propotype mapper, VERSE, and tested on several common synthesis benchmarks.