A DSL compiler for accelerating image processing pipelines on FPGAs

• Published in: 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) pp. 327 - 338
• Main Authors: Chugh, Nitin, Vasista, Vinay, Purini, Suresh, Bondhugula, Uday
• Format: Conference Proceeding
• Language: English
• Published: ACM 11.09.2016
• Subjects: DSL; Field programmable gate arrays; Image processing; Optimization; Pipeline processing; Pipelines
• DOI: 10.1145/2967938.2967969

This paper describes an automatic approach to accelerate image processing pipelines using FPGAs. An image processing pipeline can be viewed as a graph of interconnected stages that processes images successively. Each stage typically performs a point-wise, stencil, or other more complex operations on image pixels. Recent efforts have led to the development of domain-specific languages (DSL) and optimization frameworks for image processing pipelines. In this paper, we develop an approach to map image processing pipelines expressed in the PolyMage DSL to efficient parallel FPGA designs. Our approach exploits reuse and available memory bandwidth (or chip resources) maximally. When compared to Darkroom, a state-of-the-art approach to compile high-level DSL to FPGAs, our approach (a) leads to designs that deliver significantly higher throughput, and (b) supports a greater variety of filters. Furthermore, the designs we generate obtain an improvement even over pre-optimized FPGA implementations provided by vendor libraries for some of the benchmarks.