Buffer Design and Assignment for Structured ASIC

• Published in: Journal of Information Science and Engineering Vol. 30; no. 1; pp. 107 - 124
• Main Authors: 許博揚(Po-Yang Hsu), 劉一宇(Yi-Yu Liu)
• Format: Journal Article
• Language: English
• Published: Taipei 社團法人中華民國計算語言學學會 01.01.2014; Institute of Information Science, Academia sinica
• Subjects: Applied sciences; Buffers; Channels; Circuit design; Delay; Electronics; Exact sciences and technology; Insertion; Integrated circuits; Integrated circuits by function (including memories and processors); Migration; Performance enhancement; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Wire; structured ASIC; via patterned gate array; channel migration; timing optimization; buffer assignment; Circuit design; Saturation; Insertion; Routing; Layout problem; Buffer system; Wire; Timed system; Optimization; Delay; Delay circuit; Forwarding; Buffer circuits; Capacitance; Custom circuit
• ISSN: 1016-2364
• DOI: 10.6688/JISE.2014.30.1.6

In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insertion issues in structured ASIC design style. We design the layout for two dedicated buffers and extract the technology-dependent parameters for evaluation. Furthermore, we propose post-routing channel migration techniques, which employ intra-channel migration and inter-channel migration, to deal with the sub-channel saturation problem during buffer assignment. Compared to the baseline designs with 4X-buffer at the CLB output, our proposed structured ASIC design and optimization techniques improve the circuit performance by 65.7% and the ratio of wire delay to gate delay from 8.2 to 0.8.