Hardware Trojan horse detection using gate-level characterization

• Published in: 2009 46th ACM/IEEE Design Automation Conference pp. 688 - 693
• Main Authors: Potkonjak, Miodrag, Nahapetian, Ani, Nelson, Michael, Massey, Tammara
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 26.07.2009; IEEE
• Series: ACM Conferences
• Subjects: Application software; Data privacy; Data security; Foundries; gate-level characterization; Hardware; Hardware > Integrated circuits; Hardware Trojan horses; Invasive software; linear programming; Manufacturing; manufacturing variability; Research and development; Software libraries; Testing; gate-level characterization; Hardware Trojan horses; linear programming; manufacturing variability
• ISBN: 9781605584973; 1605584975
• ISSN: 0738-100X
• DOI: 10.1145/1629911.1630091

Hardware Trojan horses (HTHs) are the malicious altering of hardware specification or implementation in such a way that its functionality is altered under a set of conditions defined by the attacker. There are numerous HTHs sources including untrusted foundries, synthesis tools and libraries, testing and verification tools, and configuration scripts. HTH attacks can greatly comprise security and privacy of hardware users either directly or through interaction with pertinent systems and application software or with data. However, while there has been a huge research and development effort for detecting software Trojan horses, surprisingly, HTHs are rarely addressed. HTH detection is a particularly difficult task in modern and pending deep submicron technologies due to intrinsic manufacturing variability. Our goal is to provide an impetus for HTH research by creating a generic and easily applicable set of techniques and tools for HTH detection. We start by introducing a technique for recovery of characteristics of gates in terms of leakage current, switching power, and delay, which utilizes linear programming to solve a system of equations created using non-destructive measurements of power or delays. This technique is combined with constraint manipulation techniques to detect embedded HTHs. The effectiveness of the approach is demonstrated on a number of standard benchmarks.