Exploring serial vertical interconnects for 3D ICs

• Published in: 2009 46th ACM/IEEE Design Automation Conference pp. 581 - 586
• Main Author: Pasricha, Sudeep
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 26.07.2009; IEEE
• Series: ACM Conferences
• Subjects: 3D ICs; Delay; Hardware > Emerging technologies; Hardware > Very large scale integration design; Integrated circuit interconnections; Network-on-a-chip; Networks on Chip; Power system interconnection; Repeaters; Serial Interconnect; Silicon; Stacking; Three-dimensional integrated circuits; Through-silicon vias; VLSI; Wire; networks on chip; serial interconnect; VLSI; 3D ICs
• ISBN: 9781605584973; 1605584975
• ISSN: 0738-100X
• DOI: 10.1145/1629911.1630061

Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-chip communication bottleneck and improve performance over traditional two-dimensional (2D) ICs. Long interconnects can be replaced by much shorter vertical through silicon via (TSV) interconnects in 3D ICs. This enables faster and more power efficient inter-core communication across multiple silicon layers. However, 3D IC technology also faces challenges due to higher power densities and routing congestion due to TSV pads distributed on each layer. In this paper, serialization of vertical TSV interconnects in 3D ICs is proposed as one way to address these challenges. Such serialization reduces the interconnect TSV footprint on each layer. This can lead to a better thermal TSV distribution resulting in lower peak temperatures, as well as more efficient core layout across multiple layers due to the reduced congestion. Experiments with several 3D multi-core benchmarks indicate clear benefits of serialization. For instance, a 4:1 serialization of TSV interconnects can save more than 70% of TSV area footprint at a negligible performance and power overhead at the 65nm technology node.