A Complete Network-On-Chip Emulation Framework

• Published in: Design, Automation and Test in Europe pp. 246 - 251
• Main Authors: Genko, N., Atienza, D., Micheli, G. De, Mendias, J. M., Hermida, R., Catthoor, F.
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 07.03.2005; IEEE
• Series: ACM Conferences
• Subjects: Computer systems organization > Architectures > Other architectures > Reconfigurable computing; Computer systems organization > Architectures > Other architectures > Self-organizing autonomic computing; Concrete; Emulation; Field programmable gate arrays; Hardware > Communication hardware, interfaces and storage > Buses and high-speed links; Hardware > Hardware validation > Functional verification > Simulation and emulation; Hardware > Very large scale integration design > Application-specific VLSI designs; Hardware design languages; Network topology; Network-on-a-chip; Networks > Network protocols; Scalability; Silicon; Switches; Testing
• ISBN: 9780769522883; 0769522882
• ISSN: 1530-1591
• DOI: 10.1109/DATE.2005.5

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.