Optimal placement of power supply pads and pins

Power delivery networks of VLSI chips require adequate input supply connections to ensure reliable performance. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power supply network, subject to constraints on the...

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Bibliographic Details
Published in2004 41st Conference Design Automation pp. 165 - 170
Main Authors Zhao, Min, Fu, Yuhong, Zolotov, Vladimir, Sundareswaran, Savithri, Panda, Rajendran
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 07.06.2004
IEEE
Association for Computing Machinery
SeriesACM Conferences
Subjects
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ISBN1581138288
9781581138283
1511838288
ISSN0738-100X
DOI10.1145/996566.996615

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Summary:Power delivery networks of VLSI chips require adequate input supply connections to ensure reliable performance. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins and regulators. The problem is modeled as a mixed integer linear program using macromodeling techniques and several heuristic techniques are proposed to make the problem tractable. The effectiveness of the proposed techniques is demonstrated on several real chips and memories used in low-power and high-performance applications.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
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ISBN:1581138288
9781581138283
1511838288
ISSN:0738-100X
DOI:10.1145/996566.996615