Optimal placement of power supply pads and pins
Power delivery networks of VLSI chips require adequate input supply connections to ensure reliable performance. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power supply network, subject to constraints on the...
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Published in | 2004 41st Conference Design Automation pp. 165 - 170 |
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Main Authors | , , , , |
Format | Conference Proceeding |
Language | English |
Published |
New York, NY, USA
ACM
07.06.2004
IEEE Association for Computing Machinery |
Series | ACM Conferences |
Subjects | |
Online Access | Get full text |
ISBN | 1581138288 9781581138283 1511838288 |
ISSN | 0738-100X |
DOI | 10.1145/996566.996615 |
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Summary: | Power delivery networks of VLSI chips require adequate input supply connections to ensure reliable performance. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins and regulators. The problem is modeled as a mixed integer linear program using macromodeling techniques and several heuristic techniques are proposed to make the problem tractable. The effectiveness of the proposed techniques is demonstrated on several real chips and memories used in low-power and high-performance applications. |
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Bibliography: | SourceType-Conference Papers & Proceedings-1 ObjectType-Conference Paper-1 content type line 25 |
ISBN: | 1581138288 9781581138283 1511838288 |
ISSN: | 0738-100X |
DOI: | 10.1145/996566.996615 |