A Flexible ASIC-Oriented Design for a Full NTRU Accelerator

• Published in: 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC) pp. 591 - 597
• Main Authors: Antognazza, Francesco, Barenghi, Alessandro, Pelosi, Gerardo, Susella, Ruggero
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 16.01.2023
• Series: ACM Conferences
• Subjects: Asia; Design automation; Encapsulation; Key Encapsulation Mechanism; Libraries; NTRU; Post-quantum cryptography; Public key; Security and privacy > Security in hardware > Hardware security implementation; Space exploration; Standardization; key encapsulation mechanism; NTRU; post-quantum cryptography
• ISBN: 9781450397834; 1450397832
• ISSN: 2153-697X
• DOI: 10.1145/3566097.3567916

Post-quantum cryptosystems are the subject of a significant research effort, witnessed by various international standardization competitions. Among them, the NTRU Key Encapsulation Mechanism has been recognized as a secure, patent-free, and efficient public key encryption scheme. In this work, we perform a design space exploration on an FPGA target, with the final goal of an efficient ASIC realization. Specifically, we focus on the possible choices for the design of polynomial multipliers with different memory bus widths to trade-off lower clock cycle counts with larger interconnections. Our design outperforms the best FPGA synthesis results at the state of the art, and we report the results of ASIC syntheses minimizing latency and area with a 40nm industrial grade technology library. Our speed-oriented design computes an encapsulation in 4.1 to 10.2μs and a decapsulation in 7.1 to 11.7μs, depending on the NTRU security level, while our most compact design only takes 20% more area than the underlying SHA-3 hash module.